A common method of designing an integrated circuit (IC) may utilize a library of standard cells and a behavioral circuit model for describing the functionality of the IC. The standard cells typically include fundamental logic gates such as OR, NAND, NOR, AND, XOR, inverter, and like logical cells with an array of logic gate sizes. These cells also include sequential circuit elements such as latches and flip-flops for memory requirements. Generally, the library of standard cells are generated by a layout designer manually.
To design the ICs to utilize less area, high density standard cell libraries with area-efficient circuits may be used to help reduce area at block level. In design rule check (DRC) stringent technologies, each and every metal connection used in a layout causes routing congestion and results in higher area at the block level. Therefore, to improve (or, alternatively, optimize) the area at cell level, each and every circuit may need to be studied in an attempt to reduce (or, alternatively, minimize) the number of connections and improve (or, alternatively, maximize) the power sharing in layouts.
FIG. 1 illustrates a conventional full adder (ADDF) circuit, wherein the conventional ADDF circuit includes 8 transmission gates (TGs) and 7 inverters.
The conventional ADDF is based on the TGs, wherein an input A, B or CI is not directly given to the TGs, so that input capacitance for the circuit is constant and not changing with the input condition. Further, the conventional ADDF may utilize buffers for the inputs, which may increase area overhead. Further, the inputs are transmitted through the TGs depending upon the inputs. Due to large number of the TGs, there are extra metal connections in the layout which results in an area penalty. Depending upon the input signal conditions some of the transmission gates are ON and an input signal is transmitted and output summation (SUM) and carryout (CO) signals are generated.
FIG. 2 illustrates a conventional four input multiplexer (MXT4), where the input is inverted and transmitted through different TGs based on selection input signals. Due to a large number of TGs present in the conventional MXT4, there may be a large number of metal connections and a large routing complexity thus leading to area overhead. The conventional MXT4 has 6 input signals A, B, C, D, S0 and S1. Hence depending upon the 4 input combinations of S0 and S1 signals, one of the input (A, B, C, D) signals goes to the output Y. Further, depending on the combination of S0 and S1, transmission gates are ON and input is transmitted to the output Y.